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ADP3207C 7-Bit Programmable, Multi-Phase Mobile, CPU Synchronous Buck Controller
The ADP3207C is a high efficiency, multi-phase, synchronous, buck-switching regulator controller optimized for converting notebook battery voltage into the core supply voltage required by high performance Intel processors. The part uses an internal 7-bit Digital-to-Analog Converter (DAC) to read Voltage Identification (VID) code directly from the processor that sets the output voltage. The phase relationship of the output signals can be programmed to provide 1-, 2-, or 3-phase operation, allowing for the construction of up to three interleaved buck-switching stages. The ADP3207C uses a multi-mode architecture to drive the logic-level PWM outputs at a programmable switching frequency that can be optimized depending on the output current requirement. The part switches between multi-phase and single-phase operation to maximize its effectiveness under all load conditions. In addition, the ADP3207C includes a programmable slope function to adjust the output voltage as a function of the load current. As a result, it is always best positioned for a system transient. The chip also provides accurate and reliable short-circuit protection, adjustable current limiting, and a delayed power-good output that accommodates On-the-Fly (OTF) output voltage changes requested by the CPU. The ADP3207C is specified over the extended commercial temperature range of -10C to 100C and is available in a 40-lead LFCSP. The ADP3207CF has a soft-start time one tenth of ADP3207C. There are no other differences between the ADP3207C and ADP3207CF.
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LFCSP40 CASE 932AC
MARKING DIAGRAMS
ADP3207C AWLYYWWG
ADP3207C CF AWLYYWWG
A WL YYWW G
= Assembly Location = Wafer Lot = Date Code = Pb-Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 31 of this data sheet.
* 1-, 2-, or 3-Phase Operation at Up to 750 kHz per Phase * $7 mV Worst-Case Differential Sensing Error * Input Voltage Range of 3.3 V to 22 V * Interleaved PWM Outputs for Driving External High * * * *
Overtemperature
* Independent Current Limit and Load Line Setting * * * * * *
Power MOSFET Drivers Enhanced PWM FlexModet for Excellent Load Transient Performance Automatic Power-Saving Modes Maximize Efficiency During Light Load and Deeper Sleep Operation Soft Transient Control Reduces Inrush Current and Audio Noise Active Current Balancing Between Output Phases
Inputs for Additional Design Flexibility Built-In, Power-Good Masking Supports VID OTF 7-Bit Digitally Programmable 0.3 V to 1.5 V Output Overload and Short-Circuit Protection Latchoff Delay Built-In, Clock Enable Output Delays CPU Clock Until CPU Supply Voltage Stabilizes Current Monitor Output Signals the Total Output Power of the Buck Converter This is a Pb-Free Device
Applications
* Notebook Power Supplies for Next Generation
Intel(R) Processors
(c) Semiconductor Components Industries, LLC, 2009
December, 2009 - Rev. 0
1
Publication Order Number: ADP3207C/D
ADP3207C
VARFREQ RAMP GND RPM
VCC
EN
UVLO Shutdown and Bias COMP FB - + + REF LLINE + S - + S + _ 1.7V - CSREF + - SW1 Thermal Throttle Control SW2 SW3 OVP VEA Current Balancing Circuit Oscillator Driver Logic PWM1 PWM2 PWM3 OD DCM
PSI TTSNS VRTT
DAC - 200 mV - CSREF +
OCP Shutdown Delay DPRSTP DPRSLP DPRSLP Logic DPRSTP DPRSTP
- + DAC - 300 mV PWRGD Open Drain PWRGD Startup Delay
Logic Current Limit Current Circuit Monitor
SP Current IMON Monitor
RT
IMON
PWRGD
Soft Transient Delay Delay CLKEN Startup Delay Disable
+ -
CSREF CSSUM CSCOMP ILIMN ILIMP
CLKEN
CLKEN Open Drain Precision Reference
FBRTN
VID DAC DAC REF
Soft-Start Soft Transient
Figure 1. Functional Block Diagram
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IREF
VID6
VID5
VID4
VID3
VID2
VID1
VID0
ADP3207C
ABSOLUTE MAXIMUM RATINGS
Parameter VCC FBRTN SW1 to SW3 DC t < 200 ns RAMPADJ (In Shutdown) All Other Inputs and Outputs Storage Temperature Range Operating Ambient Temperature Range Operating Junction Temperature Thermal Impedance (qJA) Lead Temperature Soldering (10 sec) Infrared (15 sec) Rating -0.3 to +6.0 -0.3 to +0.3 -5 to +22 -10 to +28 -0.3 to +22 -0.3 to VCC + 0.3 -65 to +150 -10 to 100 125 98 300 260 Unit V V V
V V C C C C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
33 DPSTP
EN PWRGD IMON CLKEN FBRTN FB COMP NC RPM DPRSLP
1 2 3 4 5 6 7 8 9 10 ILIMP 12 ILIMN 13 RAMP 15 LLINE 16 CSSUM 18 CSCOMP 19 CSREF 17 GND 20 IREF 11 RT 14
31 VCC 30 29 28 27
40 VID0
39 VID1
38 VID2
37 VID3
36 VID4
35 VID5
34 VID6
32 PSI
TTSN VRTT DCM OD PWM1 PWM2 PWM3 SW1 SW2 SW3
ADP3207C
26 25 24 23 22 21
Figure 2. Pin Configuration
(Top View)
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ADP3207C
PIN FUNCTION DESCRIPTIONS
Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Mnemonic EN PWRGD IMON CLKEN FBRTN FB COMP NC RPM DPRSLP IREF ILIMP ILIMN RT RAMPADJ LLSET CSREF Description Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low. Power-Good Output. Open-drain output that signals when the output voltage is outside of the proper operating range. The pull-high voltage on this pin cannot be higher than VCC. Current Monitor Output. This pin sources a current proportional to the output load current. A resistor to FBRTN sets the current monitor gain. Clock Enable Output. The pull-high voltage on this pin cannot be higher than VCC. Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage. Feedback Input. Error amplifier input for remote sensing of the output voltage. Error Amplifier Output and Compensation Point. Not Connected. RPM Mode Timing Control Input. A resistor between this pin to ground sets the RPM mode turn-on threshold voltage. Deeper Sleep Control Input. This pin sets the internal bias currents. A 80kW resistor is connected from this pin to ground. Current Limit Set. An external resistor from ILIMN to ILIMP sets the current limit threshold of the converter. Current Limit Set. An external resistor from ILIMN to ILIMP sets the current limit threshold of the converter. Multi-phase Frequency Setting Input. An external resistor connected between this pin and GND sets the oscillator frequency of the device when operating in multi-phase PWM mode. PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal PWM ramp. Output Load Line Programming Input. The center point of a resistor divider between CSREF and CSCOMP is connected to this pin to set the load line slope. Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense amplifier and the power-good and crowbar functions. This pin should be connected to the common point of the output inductors. Current Sense Summing Node. External resistors from each switch node to this pin sum the inductor currents together to measure the total output current. Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determine the gain of the current sense amplifier and the positioning loop response time. Ground. All internal biasing and the logic output signals of the device are referenced to this ground. Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases should be left open. Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver, such as the ADP3611. Connecting the PWM2 and/or PWM3 outputs to VCC causes that phase to turn off, allowing the ADP3207C to operate as a 1-, 2-, or 3-phase controller. Multi-phase Output Disable Logic Output. This pin is actively pulled low when the ADP3207C enters single-phase mode or during shutdown. Connect this pin to the SD inputs of the Phase 2 and Phase 3 MOSFET drivers. Discontinuous Current Mode Enable Output. This pin is actively pulled low when the single-phase inductor current crosses zero. Voltage Regulator Thermal Throttling Logic Output. This pin goes high if the temperature at the monitoring point connected to TTSENSE exceeds the programmed VRTT temperature threshold. Thermal Throttling Sense Input and OVP Disable. The center point of a resistor divider (where the lower resistor is an NTC thermistor) between VCC and GND is connected to this pin to remotely sense the temperature at the desired thermal monitoring point. Connect TTSENSE VCC if Thermal Throttling is not used. Supply Voltage for the Device. Power State Indicator Input. Pulling this pin to GND forces the ADP3207C to operate in single-phase mode. Deeper Stop Control Input. Voltage Identification DAC Inputs. When in normal operation mode, the DAC output programs the FB regulation voltage from 0.3 V to 1.5 V (see Table 3).
18 19 20 21 to 23 24 to 26 27
CSSUM CSCOMP GND SW3 to SW1 PWM3 to PWM1 OD
28 29 30
DCM VRTT TTSENSE
31 32 33 34 to 40
VCC PSI DRPSTP VID6 to VID0
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ADP3207C
ELECTRICAL CHARACTERISTICS VCC = 5.0 V, FBRTN = GND, EN = VCC, VVID = 0.50 V to 1.5000 V, PSI = 1.05 V, DPRSLP = GND, DPRSTP= 1.05 V, LLSET = CSREF, TA = -10C to 100C, unless otherwise noted (Note 1). RREF = 80 kW. Current entering a pin (sunk by the device) has a positive sign.
Parameter FB, LLINE Voltage Range (Note 2) FB, LLINE Offset Voltage (Note 2) FB Bias Current (Note 2) LLINE Bias Current (Note 2) LLINE Positioning Accuracy COMP Voltage Range COMP Current Symbol VFB, VLLINE VOSVEA IFB ILL VFB - VVID VCOMP ICOMP Measured on FB relative to VVID, LLINE forced 80 mV below CSREF Operating Range COMP = 2.0 V, CSREF = VDAC FB forced 200 mV below CSREF FB forced 200 mV above CSREF CCOMP = 10 pF, CSREF = VDAC, Open loop configuration FB forced 200 mV below CSREF FB forced 200 mV above CSREF Non-inverting unit gain configuration, RFB = 1 kW See VID Code Table VFB - VVID Measured on FB (includes offset), relative to VVID, for VID table see Table 3, TA = -10C to 85C VVID = 1.2125 V to 1.5000 V VVID = 0.3000 V to 1.2000 V VCC = 4.75 V to 5.25 V Measured during boot delay period Measured from EN pos edge to FB = 50 mV Measured from EN pos edge to FB settles to VBOOT = 1.2 V within -5% ADP3207C ADP3207CF Measured from FB settling to VBOOT = 1.2 V within -5% to CLKEN neg edge Soft-Start ADP3207C Soft-Start ADP3207CF Non-LSB VID step, DPRSLP = H, Slow C4 Entry/Exit Non-LSB VID step, DPRSLP = L, Fast C4 Exit IFBRTN VUVCSREF Relative to nominal DAC Voltage: = 0.5125 V to 1.5 V = 0.3 V to 0.5 V Relative to nominal DAC Voltage Relative to FBRTN 0 Conditions Relative to CSREF = VDAC Relative to CSREF = VDAC Min -200 -0.5 -1.0 -50 -78 0.85 0.75 6.0 -80 Typ Max +200 +0.5 1.0 50 -82 4.0 Unit mV mV A nA mV V mA VOLTAGE CONTROL - Voltage Error Amplifier (VEAMP)
COMP Slew Rate
SRCOMP
V/ms 15 -20 20 MHz
Gain Bandwidth (Note 2) VID DAC VOLTAGE REFERENCE VDAC Voltage Range VDAC Accuracy
GBW
1.5
V mV
-9.0 -7.0 -1.0 0.05 1.200 200
+9.0 +7.0 +1.0 LSB % V ms ms 1.4 0.14 100 0.0625 0.625 0.25 1.0 90 200 mA mV ms LSB/ ms
VDAC Differential Non-linearity (Note 2) VDAC Line Regulation VDAC Boot Voltage Soft-Start Delay (Note 2) Soft-Start Time DVFB VBOOTFB tDSS tSS
Boot Delay VDAC Slew Rate
tBOOT
FBRTN Current CSREF Undervoltage Threshold CSREF Overvoltage Threshold CSREF Crowbar Voltage Threshold
VOLTAGE MONITORING AND PROTECTION - Power Good -240 -160 150 1.65 -300 -300 200 1.7 -360 -360 250 1.75
VOVCSREF VCBCSREF
mV V
1. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC). 2. Guaranteed by design or bench characterization, not production tested.
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ADP3207C
ELECTRICAL CHARACTERISTICS VCC = 5.0 V, FBRTN = GND, EN = VCC, VVID = 0.50 V to 1.5000 V, PSI = 1.05 V, DPRSLP = GND, DPRSTP= 1.05 V, LLSET = CSREF, TA = -10C to 100C, unless otherwise noted (Note 1). RREF = 80 kW. Current entering a pin (sunk by the device) has a positive sign.
Parameter CSREF Reverse Voltage Threshold PWRGD Low Voltage PWRGD High, Leakage Current PWRGD Startup Delay PWRGD Latchoff Delay PWRGD Propagation Delay Crowbar Latchoff Delay (Note 2) PWRGD Masking Time CSREF Soft-Stop Resistance CSSUM, CSREF Common-Mode Range (Note 2) CSSUM, CSREF Offset Voltage CSSUM Bias Current CSREF Bias Current CSCOMP Voltage Range (Note 2) CSCOMP Current ICSCOMPsource ICSCOMPsink VOSCSA IBCSSUM IBCSREF Operating Range CSCOMP = 2.0 V CSSUM forced 200 mV below CSREF CSSUM forced 200 mV above CSREF CCSCOMP = 10 pF, Open Loop Configuration CSSUM forced 200 mV below CSREF CSSUM forced 200 mV above CSREF GBWCSA Non-inverting unit gain configuration RFB = 1 kW Symbol VRVCSREF Conditions Relative to FBRTN, Latchoff mode: CSREF Falling CSREF Rising IPWRGD(SINK) = 4 mA VPWRDG = 5.0 V Measured from CLKEN neg edge to PWRGD Pos Edge Measured from Out-off-Good-Window event to Latchoff (switching stops) Measured from Out-off-Good-Window event to PWRGD neg edge Measured from Crowbar event to Latchoff (switching stops) Triggered by any VID change or OCP event EN = L or Latchoff condition 8.0 8.0 200 200 100 70 Min Typ Max Unit mV -5.0 150 1.0 mV mA ms ms ns ns ms W VOLTAGE MONITORING AND PROTECTION - Power Good -350 -300 -70 85
VPWRGD IPWRGD TSSPWRGD TLOFFPWRGD TPDPWRGD TLOFFCB
CURRENT CONTROL - Current Sense Amplifier (CSAMP) Voltage range of interest CSREF - CSSUM, TA = -10C to 85C TA = 25C 0 -1.7 -0.5 -50 -50 0.05 -750 1.0 10 -10 20 2.0 +1.7 +0.5 +50 +50 2.0 V mV nA nA V mA mA V/ms
CSCOMP Slew Rate
Gain Bandwidth (Note 2)
MHz
CURRENT MONITORING AND PROTECTION Current Reference IREF Voltage Current Limiter (OCP) Current Limit Threshold VREF VLIMTH RREF = 80 kW to set IREF = 20 mA Measured from CSCOMP to CSREF, RLIM = 4.5 kW, 2-ph configuration, PSI = H 2-ph configuration, PSI = L Measured from CSCOMP to CSREF, RLIM = 4.5 kW, 3-ph configuration, PSI = H 3-ph configuration, PSI = L 1-ph configuration Measured from OCP event to PWRGD deassertion 1.55 1.6 1.65 V mV -70 -30 -70 -15 -70 -90 -45 -90 -30 -90 8.0 -115 -65 -115 -50 -115 ms
Current Limit Latchoff Delay
1. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC). 2. Guaranteed by design or bench characterization, not production tested.
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ADP3207C
ELECTRICAL CHARACTERISTICS VCC = 5.0 V, FBRTN = GND, EN = VCC, VVID = 0.50 V to 1.5000 V, PSI = 1.05 V, DPRSLP = GND, DPRSTP= 1.05 V, LLSET = CSREF, TA = -10C to 100C, unless otherwise noted (Note 1). RREF = 80 kW. Current entering a pin (sunk by the device) has a positive sign.
Parameter CURRENT MONITOR Current Gain Accuracy IMON/ILIM Measured from ILIMP to IMON ILIM = -20 mA ILIM = -10 mA Relative to FBRTN, ILIMP = -30 mA RT = 125 kW, VVID = 1.4000 V See also VRT(VVID) formula Operating Range TA = +25C, VVID = 1.2000 V RT = 73 kW RT = 125 kW RT = 180 kW EN = high, IRAMP = 30 mA EN = low EN = high EN = low, RAMP = 19 V VRAMP - VCOMP 9.3 9.2 1.05 1.12 0.3 1.2 10 10 10.7 10.8 1.15 1.28 3.0 V V MHz kHz Symbol Conditions Min Typ Max Unit
IMON Clamp Voltage RT Voltage PWM Clock Frequency Range (Note 2) PWM Clock Frequency
VMAXMON VRT fCLK fCLK
PULSE WIDTH MODULATOR - Clock Oscillator
1150 500 0.9 1.0 -0.5 -3.0
1450 850 630 1.0 VIN
1750 780 1.1 100 +0.5 3.0
RAMP GENERATOR RAMP Voltage RAMP Current Range (Note 2) PWM COMPARATOR PWM Comparator Offset (Note 2) RPM COMPARATOR RPM Current RPM Comparator Offset (Note 2) EPWM CLOCK SYNC Trigger Threshold (Note 2) Relative to COMP sampled TCLK earlier 3-phase configuration 2-phase configuration 1-phase configuration VSW(X)CM RSW(X) VDCM(SW1) tOFFMSKD Operating Range for current sensing SWX = 0 V DCM mode, DPRSLP = 3.3 V Measured from PWM neg edge to PWM Pos Edge at max frequency of operation Refers to driving signal level Logic low, Isink w 1 mA Logic high, Isource v -5 mA V = 0.2 V VID[6:0], DPRSLP (active pulldown to GND) PSI (active pullup to VCC) Any VID edge to FB change 10% 200 -600 20 32 -4.0 700 300 350 400 +200 45 mV IRPM VOSRPM VVID = 1.2 V, RT = 125 kW See also IRPM(RT) formula VCOMP - (1 +VRPM) -3.0 -8.8 3.0 mA mV VOSRPM mV VRAMP IRAMP V mA
SWITCH AMPLIFIER SW Common Mode Range (Note 2) SW Input Resistance SW ZCS Threshold Masked Off Time mV kW mV ns
ZERO CURRENT SWITCHING COMPARATOR
SYSTEM I/O BUFFERS VID[6:0], PSI INPUTS Input Voltage 0.3 V
0.7 -1.0 +2.0
Input Current
mA
VID Delay Time (Note 2)
ns
1. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC). 2. Guaranteed by design or bench characterization, not production tested.
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ADP3207C
ELECTRICAL CHARACTERISTICS VCC = 5.0 V, FBRTN = GND, EN = VCC, VVID = 0.50 V to 1.5000 V, PSI = 1.05 V, DPRSLP = GND, DPRSTP= 1.05 V, LLSET = CSREF, TA = -10C to 100C, unless otherwise noted (Note 1). RREF = 80 kW. Current entering a pin (sunk by the device) has a positive sign.
Parameter DPRSLP Input Voltage Refers to driving signal level Logic low, Isink w 1 mA Logic high, Isource v -5 mA DPRSLP = low DPRSLP = high Refers to driving signal level Logic low, Isink w 1 mA Logic high, Isource v -5 mA 0.4 -1.0 +2.0 V Symbol Conditions Min Typ Max Unit
2.3
Input Current DPRSTP Input Voltage (Note 2)
mA
0.7 1.0
0.3
V
Input Current (Note 2) EN INPUT Input Voltage Refers to driving signal level Logic low, Isink w 1 mA Logic high, Isource v -5 mA EN = L or EN = H (Static) 0.8 V < EN < 1.6 V (During Transition) Logic low, Isink = 4 mA Logic high, VCLKEN = VCC
mA V
2.3 10 70 30
0.3
Input Current CLKEN OUTPUT Output Low Voltage Output High, Leakage Current THERMAL MONITORING AND PROTECTION TTSNS Voltage Range (Note 2) TTSNS Threshold TTSNS Bias Current VRTT Output Voltage TTSNS Hysteresis PWM, OD, AND DCM OUTPUT Output Low Voltage SUPPLY Supply Voltage Range Supply Current VCC OK Threshold VCC UVLO Threshold VCC Hysteresis (Note 2) VCCOK VCCUVLO VCC VVRTT
nA mA 200 1.0 mV mA
0 VCC = 5.0 V, TTSNS is falling TTSNS = 2.6 V Logic low, IVRTT(SINK) = 400 mA Logic high, IVRTT(SOURCE) = -400 mA 2.45 -2.0 4.0 50 Logic Low, ISINK = 400 mA Logic High, ISOURCE = -400 mA 10 5.0 100 10 5.0 2.5
5.0 2.55 2.0 50
V V mA mV V mV
4.0 4.5
200
mV V V mA mA V V mV
5.5 6.0 20 4.4 10 100 4.5
EN = H EN = 0 V VCC is Rising VCC is Falling 4.0
4.15 150
1. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC). 2. Guaranteed by design or bench characterization, not production tested.
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ADP3207C
TEST CIRCUITS
5.0 V DPSTP PSI VID0 VID1 VID2 VID3 VID4 VID5 1 EN VID6 VCC 1 mF
3.3 V
TTSN VRTT DCM OD 5.0 V 31 VCC CSCOMP ADP3207C
PWRGD IMON CLKEN FBRTN FB COMP 1 kW NC CSCOMP RPM RAMP LLINE ILIMP CSREF ILIMN IREF DPRSLP CSSUM ADP3207C
PWM1 PWM2 PWM3 SW1 SW2 GND SW3 1 kW 39 kW 10 nF
19
18 17 1.0 V 20
CSSUM CSREF
- + CSCOMP * 1.0 V 40 V
RT
1 kW
GND
V
OS
+
100 nF
Figure 3. Closed-Loop Output Voltage Accuracy
Figure 4. Current Sense Amplifier VOS
5.0 V 31
VCC
ADP3207C
COMP 7 10 kW 6 FB - + LLINE 16 DV - + 17 1.0 V + - 20 DV CSREF VID DAC + -
GND + FB + DELATV * FB
FB
DV
DV+0 mV
Figure 5. Positioning Accuracy
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ADP3207C
TYPICAL PERFORMANCE CHARACTERISTICS
PWRGD
CLKEN ENABLE ENABLE
CLKEN
PWRGD
OUTPUT VOLTAGE OUTPUT VOLTAGE
Figure 6. ADP3207CF Startup
1000 CLKEN SWITCHING FREQUENCY (kHz)
Figure 7. ADP3207C Startup
VID = 1.4125 V 1.2125 V 1.1 V 0.8125 V
ENABLE
PWRGD
OUTPUT VOLTAGE
0.6125 V
100 10
2-Phase Configuration 100 Rt, RESISTANCE (kW) 1000
Figure 8. ADP3207C Startup
Figure 9. Per Phase Switching Frequency vs. RT Resistance
OUTPUT VOLTAGE
OUTPUT VOLTAGE
SW3
SW3
SW2
SW2
SW1
SW1
Input = 12 V 9 A to 44 A
Figure 10. Load Transient
Figure 11. Load Transient
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ADP3207C
TYPICAL PERFORMANCE CHARACTERISTICS
OUTPUT VOLTAGE SW3 SW3 SW2 SW2 SW1
OUTPUT VOLTAGE
SW1
Input = 12 V 44 A to 9 A
Input = 12 V 2 A to 12 A
Figure 12. Load Transient
Figure 13. Single Phase Load Transient
OUTPUT VOLTAGE
OUTPUT VOLTAGE
SW3 SW2 SW1
SW3 SW2 SW1
Input = 12 V 12 A to 2 A
Input = 12 V 2 A to 12 A
Figure 14. Single Phase Load Transient
Figure 15. Single Phase Load Transient
OUTPUT VOLTAGE PSI
OUTPUT VOLTAGE
PSI SW1 SW3 SW2 SW1 SW3 SW2
Input = 12 V Output = 1.0 V No Load DPRSLP = Low
Input = 12 V Output = 1.0 V No Load DPRSLP = Low
Figure 16. PSI Transition
Figure 17. PSI Transition
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ADP3207C
TYPICAL PERFORMANCE CHARACTERISTICS
OUTPUT VOLTAGE
OUTPUT VOLTAGE
DPRSLP SW1 SW3 SW2
DPRSLP SW1 SW3 SW2
Input = 12 V Output = 1.0 V 1 A Load PSI = Low
Input = 12 V Output = 1.0 V 1 A Load PSI = Low
Figure 18. DPRSLP Transition
Figure 19. DPRSLP Transition
OUTPUT VOLTAGE
OUTPUT VOLTAGE
DPRSLP SW1 SW3 SW2 SW1 SW3 SW2
DPRSLP
Input = 12 V Output = 1.0 V 1 A Load PSI = High
Input = 12 V Output = 1.0 V 1 A Load PSI = High
Figure 20. DPRSLP Transition
Figure 21. DPRSLP Transition
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ADP3207C
TYPICAL PERFORMANCE CHARACTERISTICS
300 SWITCHING FREQUENCY (kHz) 250 200 150 100 50 0 Switching Frequency 10 A Load (CCM) Output Ripple 24 A Load (DCM) Output Ripple 10 A Load (DCM) 30 25 20 15 10 Output = 1.0 V PSI = High DRPSLP = Low 5 0 20 OUTPUT RIPPLE (mV) OUTPUT RIPPLE (mV)
Switching Frequency 2 A Load (DCM)
5
10 15 INPUT VOLTAGE (V)
Figure 22. Switching Frequency and Output Ripple in RPM
350 SWITCHING FREQUENCY (kHz) 300 250 200 150 100 Output Ripple 50 0 0 0.25 Input = 12 V 10 A Load DRPSLP = Low 1.25 Switching Frequency
35 30 25 20 15 10 5 0 1.5
0.5 0.75 1 OUTPUT VOLTAGE (V)
Figure 23. Switching Frequency and Output Ripple in RPM
300 SWITCHING FREQUENCY (kHz) 250 200 150 100 50 0 0 Input = 12 V Output = 1.0 V DRPSLP = Low 2 4 6 8 RPM = 71.5 W RT = 110 kW RAMP = 499 kW 10 12 14 16 SWITCHING FREQUENCY (kHz) 500 450 400 350 300 250 200 150 100 50 0 0 Input = 12 V PSI = High DRPSLP = High 3-Phase 0.25 0.5 0.75 Output Ripple Switching Frequency 10 9 8 7 6 5 4 3 2 1 1 1.25 0 1.5 OUTPUT RIPPLE (mV)
LOAD CURRENT (A)
OUTPUT VOLTAGE (V)
Figure 24. Switching Frequency in RPM
Figure 25. Switching Frequency in PWM
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ADP3207C
Theory of Operation The ADP3207C combines a multi-mode Ramp Pulse Modulated (PWM/RPM) control with multi-phase logic outputs for use in 1-, 2-, and 3-phase synchronous buck CPU core supply power converters. The internal 7-bit VID DAC conforms to Intel IMVP-6 specifications. Multi-phase operation is important for producing the high currents and low voltages demanded by today's microprocessors. Handling high currents in a single-phase converter puts high thermal stress on the system components, such as the inductors and MOSFETs. The multi-mode control of the ADP3207C ensures a stable high performance topology for: * Balancing currents and thermals between phases * High speed response at the lowest possible switching frequency and minimal output decoupling * Minimizing thermal switching losses due to lower frequency operation * Tight load line regulation and accuracy * High current output by supporting up to 3-phase operation * Reduced output ripple due to multi-phase ripple cancellation * High power conversion efficiency both at heavy load and light load * PC board layout noise immunity * Ease of use and design due to independent component selection * Flexibility in operation by allowing optimization of design for low cost or high performance
Number of Phases
5.0 V rail function as normal PWM outputs. The pins that are connected to VCC enter into high impedance state. The PWM outputs are 5.0 V logic-level signals intended for driving external gate drivers, such as the ADP3611. Because each phase is monitored independently, operation approaching 100% duty cycle is possible. In addition, more than one output can operate at a time to allow overlapping phases.
Operation Modes
The number of operational phases and their phase relationship is determined by internal circuitry that monitors the PWM outputs. Normally, the ADP3207C operates as a 3-phase controller. For 2-phase operation, the PWM3 pin is connected to VCC 5.0 V programs, and for 1-phase operation, the PWM3 and PWM2 pins are connected to VCC 5.0 V programs. When the ADP3207C is initially enabled, the controller sinks 50 mA on the PWM2 and PWM3 pins. An internal comparator checks the voltage of each pin against a high threshold of 3.0 V. If the pin voltage is high due to pullup to the VCC 5.0 V rail, then the phase is disabled. The phase detection is made during the first three clock cycles of the internal oscillator. After phase detection, the 50 mA current sink is removed. The pins that are not connected to the VCC
For the ADP3207C, the number of phases can be selected by the user as described in the Number of Phases section, or they can dynamically change based on system signals to optimize the power conversion efficiency at heavy and light CPU loads. During a VID transient or at a heavy load condition, indicated by DPRSLP going low and PSI going high, the ADP3207C runs in full-phase mode. All user-selected phases operate in interleaved PWM mode, which results in minimal VCore ripple and best transient performance. While in light load mode, indicated by either PSI going low or DPRSLP going high, only Phase 1 of the ADP3207C is in operation to maximize power conversion efficiency. In addition to the change of phase number, the ADP3207C dynamically changes operation modes. In multi-phase operation, the ADP3207C runs in PWM mode, with switching frequency controlled by the master clock. In single-phase mode based on the PSI signal, the ADP3207C switches to RPM mode, where the switching frequency is no longer controlled by the master clock, but by the ripple voltage appearing on the COMP pin. The PWM1 pin is set to high each time the COMP pin voltage rises to a limit determined by the VID voltage and programmed by the external resistor connected between Pin VRPM and Pin RRPM. In single-phase mode based on the DPRSLP signal, the ADP3207C runs in RPM mode, with the synchronous rectifier (low-side) MOSFETs of Phase 1 being controlled by the DCM pin to prevent any reverse inductor current. Thus, the switch frequency varies with the load current, resulting in maximum power conversion efficiency in deeper sleep mode of CPU operation. In addition, during any VID transient, system transient (entry/exit of deeper sleep), or current limit, the ADP3207C goes into full phase mode, regardless of DPRSLP and PSI signals, eliminating current stress to Phase 1. Table 1 summarizes how the ADP3207C dynamically changes phase number and operation modes based on system signals and operating conditions.
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Table 1. Phase Number and Operation Modes
PSI DNC 1 0 0 DNC DNC DPRSLP DNC 0 0 0 1 1 VID Transient Period (Note 1) Yes No No No No No Hit Current Limit DNC DNC No Yes No Yes No. of Phases Selected by User N 3, 2, or 1 N 3, 2, or 1 DNC DNC DNC DNC No. of Phases in Operation N N Phase 1 only N Phase 1 only N Operation Mode PWM, CCM Only PWM, CCM Only RPM, CCM Only PWM, CCM Only RPM, Automatic CCM / DCM PWM, CCM Only
1. VID transient period is the time following any VID change, including entrance and exit of deeper sleep mode. The duration of VID transient period is the same as that of PWRGD masking time. 2. DNC = Do Not Care. 3. CCM = Continuous Conduction Mode. 4. DCM = Discontinuous Conduction Mode.
Switch Frequency Setting
Master Clock Frequency for PWM Mode
The clock frequency of the ADP3207C is set by an external resistor connected from the RT pin to ground. The frequency varies with the VID voltage; the lower the VID voltage, the lower the clock frequency. The variation of clock frequency with VID voltage makes VCore ripple remain constant and improves power conversion efficiency at a lower VID voltage. To determine the switching frequency per phase, the clock is divided by the number of phases in use. If PWM3 is pulled up to VCC, then the master clock is divided by 2 for the frequency of the remaining phases. If PWM2 and PWM3 are pulled up to VCC, then the switching frequency of a Phase 1 equals the master clock frequency. If all phases are in use, divide by 3.
Switching Frequency for RPM Mode-Phase 1
The CPU core output voltage is sensed between the FB pin and the FBRTN pin. Connect FB through a resistor to the positive regulation point, usually the VCC remote sense pin of the microprocessor. Connect FBRTN directly to the negative remote sense point, the VSS sense point of the CPU. The internal VID DAC and precision voltage reference are referenced to FBRTN and have a maximum current of 200 mA to guarantee accurate remote sensing.
Output Current Sensing
When ADP3207C operates in single-phase RPM mode, its switching frequency is not controlled by the master clock, but by the ripple voltage on the COMP pin. The PWM1 pin is set high each time the COMP pin voltage rises to a voltage limit determined by the VID voltage and the external resistance connected between Pin RPM and ground. Whenever PWM1 pin is high, an internal ramp signal rises at a slew rate programmed by the current flowing into the RAMP pin. Once this internal ramp signal hits the COMP pin voltage, the PWM1 pin is reset to low. In continuous current mode, the switching frequency of RPM operation is maintained almost constantly. While in discontinuous current mode, the switching frequency reduces with the load current.
Output Voltage Differential Sensing
The ADP3207C combines differential sensing with a high accuracy, VID DAC, precision REF output and a low offset error amplifier to meet the rigorous accuracy requirement of the Intel IMVP-6 specification. In steady-state, the VID DAC and error amplifier meet the worst-case error specification of $10 mV over the full operating output voltage and temperature range.
The ADP3207C provides a dedicated current sense amplifier (CSA) to monitor the total output current of the converter for proper voltage positioning vs. load current and for current limit detection. Sensing the load current being delivered to the load is inherently more accurate than detecting peak current or sampling the current across a sense element, such as the low-side MOSFET. The current sense amplifier can be configured several ways depending on system requirements, including: * Output inductor ESR sensing without use of a thermistor for lowest cost * Output inductor ESR sensing with use of a thermistor that tracks inductor temperature to improve accuracy * Discrete resistor sensing for highest accuracy The positive input of the CSA is connected to the CSREF pin, which is connected to the output voltage. At the negative input CSSUM pin of the CSA, signals from the sensing element (that is, in case of inductor RDC sensing, signals from the switch node side of the output inductors) are summed together by using series summing resistors. The feedback resistor between CSCOMP and CSSUM sets the gain of the current sense amplifier, and a filter capacitor is placed in parallel with this resistor. The current information is then given as the voltage difference between CSREF and CSCOMP. This signal is used internally as a differential input for the current limit comparator. An additional resistor divider connected between CSREF and CSCOMP with the midpoint connected to LLSET can be used to set the load line required by the microprocessor specification. The current information for load line setting is
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ADP3207C
then given as the voltage difference of CSREF - LLSET. The configuration in the previous paragraph makes it possible for the load line slope to be set independent of the current limit threshold. In the event that the current limit threshold and load line do not have to be independent, the resistor divider between CSREF and CSCOMP can be omitted and the CSCOMP pin can be connected directly to LLSET. To disable voltage positioning entirely (that is, to set no load line), tie LLSET to CSREF. To provide the best accuracy for current sensing, the CSA is designed to have a low offset input voltage. In addition, the sensing gain is set by an external resistor ratio.
Active Impedance Control Mode
amounts to achieve thermal balance starting with the coolest phase. If adjusting current balance between phases is not needed, RSW should be 1 kW for all phases.
Voltage Control Mode
To control the dynamic output voltage droop as a function of the output current, the signal proportional to the total output current is converted to a voltage that appears between CSREF and LLINE. This voltage can be scaled to equal the droop voltage, which is calculated by multiplying the droop impedance of the regulator with the output current. The droop voltage is then used as the control voltage of the PWM regulator. The droop voltage is subtracted from the DAC reference output voltage and determines the voltage positioning setpoint. The setup results in an enhanced feed forward response.
Current Control Mode and Thermal Balance
A high gain bandwidth error amplifier is used for the voltage-mode control loop. The non-inverting input voltage is set via the 7-bit VID DAC. The VID codes are listed in Table 3. The non-inverting input voltage is offset by the droop voltage as a function of current, commonly known as active voltage positioning. The output of the error amplifier is the COMP pin, which sets the termination voltage for the internal PWM ramps. The negative input, FB, is tied to the output sense location through a resistor, RB, for sensing and controlling the output voltage at the remote sense point. The main loop compensation is incorporated in the feedback network connected between FB and COMP.
Enhanced PWM Mode
The ADP3207C has individual inputs for monitoring the current in each phase. The phase current information is combined with an internal ramp to create a current balancing feedback system that is optimized for initial current accuracy and dynamic thermal balance. The current balance information is independent of the total inductor current information used for voltage positioning described in the Active Impedance Control Mode section. The magnitude of the internal ramp can be set so the transient response of the system becomes optimal. The ADP3207C also monitors the supply voltage to achieve feed-forward control whenever the supply voltage changes. A resistor connected from the power input voltage rail to the RAMP pin determines the slope of the internal PWM ramp. Detailed information about programming the ramp is given in the Ramp Resistor Selection section. External resistors are in series with the SW1 pin, SW2 pin, and the SW3 pin to create an intentional current imbalance. Such a condition can exist when one phase has better cooling and supports higher currents than the other phase. Resistor RSW2 and Resistor RSW3 (see the Typical Application Circuit in Figure 28) can be used to adjust thermal balance. It is recommended to add these resistors during the initial design to make sure placeholders are provided in the layout. To increase the current in any given phase, users should make RSW for that phase larger (that is, make RSW = 1.5 kW for the hottest phase and do not change it during balance optimization). Increasing RSW to 1.5 kW makes a substantial increase in phase current. Increase each RSW value by small
Enhanced PWM mode is intended to improve the transient response to a load step up. In traditional PWM controllers, when a load step up occurred, the controller had to wait until the next turn on of the PWM signal to respond to the load change. Enhanced PWM mode allows the controller to respond immediately when a load step up occurs. This allows the phases to respond when the load increase transition takes place. EWPM is disabled in RPM operation.
Power-Good Monitoring
The power-good comparator monitors the output voltage via the CSREF pin. The PWRGD pin is an open drain output that can be pulled up through an external resistor to a voltage rail that is not necessarily the same VCC voltage rail of the controller. Logic high level indicates that the output voltage is within the voltage limits defined by a window around the VID voltage setting. PWRGD goes low when the output voltage is outside of that window. Following the IMVP-6 specification, the PWRGD window is defined as -300 mV below and +200 mV above the actual VID DAC output voltage. For any DAC voltage below 300 mV, only the upper limit of the PWRGD window is monitored. To prevent false alarm, the power-good circuit is masked during various system transitions, including any VID change and entrance/exit out of deeper sleep. The duration of the PWRGD mask is set by an internal timer to be about 100 ms. In conditions where a larger than 200 mV voltage drop occurs during deeper sleep entry or slow deeper sleep exit, the duration of PWRGD masking is extended by an internal logic circuit.
Powerup Sequence and Soft-Start
The power-on, ramp-up time of the output voltage is set internally. The reference voltage of the voltage error amplifier is connected to an internal DAC. This DAC converts the VID
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ADP3207C
code to an analog reference voltage. During startup, the DAC ignores the VID code. The internal DAC steps through each VID code from 0 V to the boot voltage. The DAC steps to the next VID code every 16 ms. With 12.5 mV difference between VID codes, the soft-start slew rate is 12.5 mV / 16 ms or approximately 0.78 mV/ms. This gives a soft-start time of approximately 1.5 ms. After the DAC reaches the boot voltage, an internal 100 ms timer starts. This is the 100 ms boot time. After the boot time is over, the CLKEN is asserted low. The DAC then reads the VID code. There is a soft transition from the boot voltage to the VID voltage. After CLKEN is asserted low, these is an internal 8 ms timer that asserts PWRGD high. The whole powerup sequence, including soft-start, is illustrated in Figure 26. In VCC UVLO or in shutdown, PWM1, PWM2, and PWM3 are pulled low. When VCC ramps above the upper UVLO threshold and EN is asserted high, the ADP3207C enables internal bias and starts a reset cycle that lasts about 50 ms to 60 ms. Next, when initial reset is over, the chip detects the number of phases set by the user and gives a go signal to start the internal soft-start. After the CLKEN is asserted low, the ADP3207C reads the VID codes provided by the CPU on VID0 to VID6 input pins. The VCore voltage changes from VBOOT to the VID voltage by a well-controlled soft transition, as introduced in the Soft Transient section. The PWRGD signal is not asserted until there is a tCPU_PWRGD delay of approximately 8 ms, which is fixed internally by the ADP3207C. If either EN is taken low or VCC drops below the lower VCC UVLO threshold, the PWM1, PWM2, and PWM3 signals stop switching. An internal MOSFET discharges the output voltage through the CSREF pin. The internal CSREF MOSFET has a resistance of approximately 100 W.
V5_S
decrease the acoustic noise generated by the MLCC input capacitors and inductors. The soft transient feature is implemented internally. When the ADP3207C detects a new VID code, the DAC steps through each VID code until is reaches the final code. For a fast slew rate, the ADP3207C steps to the next VID code every 1 ms. This gives a fast slew rate of 12.5 mV/ms. For a slow slew rate, the ADP3207C steps to the next VID code every 4 ms. This gives a slew rate of 3.125 mV/ms. With DPRSLP asserted high, the slow slew rate is enabled. With DPRSLP asserted low, the fast slew rate is enabled. Table 2 summarizes the soft transient slew rate.
Table 2. Soft Transient Slew Rate
VID Transient Fast Exit from Deeper Sleep Slow Exit from Deeper Sleep Transient from VBOOT to VID 1. DNC = Do Not Care. DPRSLP LOW HIGH DNC (Note 1) Slew Rate +12.5 mV/ms +3.125 mV/ms $3.125 mV/ms
Current Limit
The ADP3207C compares the differential output of a current sense amplifier to a programmable current limit setpoint to provide current limiting function. The current limit set point is set with a resistor connected from ILIM pin to CSCOMP pin. This is the Rlim resistor. During normal operation, the voltage on the ILIM pin is equal to the CSREF pin. The voltage across Rlim is equal to the voltage across the current sense amplifier (from CSREF pin to CSCOMP pin). This voltage is proportional to output current. The current through Rlim is proportional to the output inductor current. The current through Rlim is compared with an internal reference current. When the Rlim current goes above the internal reference current, the ADP3207C goes into current limit. The current limit circuit is shown in Figure 11.
20 mA VI CONV - + ILIM ILIM + -
EN
VBOOT
t Soft-Start
CLA
VHID ILIM
CSA
+ -
CSREF CSSUM
VCore
tBoot
CSCOMP CLKEN RCS CCS tPWRGD Delay PWRGD RPH
L
DCR
CBULK
Figure 27. Current Limit Circuit
Figure 26. Powerup Sequence Soft Transient
The ADP3207C provides a soft transient function to reduce inrush current during various transitions, including the entrance/exit of deeper sleep and the transition from VBOOT to VID voltage. Reducing the inrush current helps
During startup when the output voltage is below 200 mV, a secondary current limit is activated. This is necessary because the voltage swing on CSCOMP cannot extend below ground. The secondary current limit circuit clamps the internal COMP voltage and sets the internal compensation ramp termination voltage at 1.5 V level. The clamp actually limits voltage drop across the low side MOSFETs through the current balance circuitry.
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ADP3207C
An inherent per phase current limit protects individual phases in case one or more phases stop functioning because of a faulty component. This limit is based on the maximum normal-mode COMP voltage. After 9 ms in current limit, the ADP3207C will latchoff. The latchoff can be reset by removing and reapplying VCC, or by recycling the EN pin low and high for a short time. The latchoff can be reset by removing and reapplying VCC, or by recycling the EN pin low and high for a short time.
Changing VID OTF
The ADP3207C is designed to track dynamically changing VID code. As a result, the converter output voltage, that is, the CPU VCC voltage, can change without the need to reset either the controller or the CPU. This concept is commonly referred to as VID OTF transient. A VID OTF can occur either under light load or heavy load conditions. The processor signals the controller by changing the VID inputs in LSB incremental steps from the start code to the finish code. The change can be either upwards or downwards steps. When a VID input changes state, the ADP3207C detects the change but ignores the new code for a minimum of 400 ns. This keep out is required to prevent reaction to false code that can occur by a skew in the VID code while the 7-bit VID input code is in transition. Additionally, the VID change triggers a PWRGD masking timer to prevent a PWRGD failure. Each VID change resets and retriggers the internal PWRGD masking timer. As listed in Table 2, during any VID transient, the ADP3207C forces a multi-phase PWM mode regardless of system input signals.
Output Crowbar
CSREF pin. Any time the CSREF pin voltage is below -300 mV, the ADP3207C triggers its RVP function by disabling all PWM outputs and setting both the DCM and OD pins low. Thus, all the MOSFETs are turned off. The reverse inductor current can be quickly reset to 0 by dumping the energy built up in the inductor into the input dc voltage source via the forward biased body diode of the high-side MOSFETs. The RVP function is terminated when the CSREF pin voltage returns above -100 mV. Occasionally, overvoltage crowbar protection results in negative VCore voltage, because turn-on of all low-side MOSFETs leads to very large reverse inductor current. To prevent damage of the CPU by negative voltage, ADP3207C keeps its RVP monitoring function alive even after OVP latchoff. During OVP latchoff, if the CSREF pin voltage drops below -300mV, then all low-side MOSFETs are turned off by setting both DCM and OD low. The DCM pin and the OD pin are set high again when CSREF voltage recovers above -100 mV.
Output Enable and UVLO
To protect the CPU load and output components of the converter, the PWM outputs are driven low, and DCM and OD are driven high (that is, commanded to turn on the low-side MOSFETs of all phases) when the output voltage exceeds an OVP threshold of 1.7 V as specified by IMVP-6. Turning on the low-side MOSFETs discharges the output capacitor as soon as reverse current builds up in the inductors. If the output overvoltage is due to a short of the high-side MOSFET, then this crowbar action current limits the input supply or causes the input rail fuse to blow, protecting the microprocessor from destruction. Once Overvoltage Protection (OVP) is triggered, the ADP3207C is latched off. The latchoff function can be reset by removing and reapplying VCC, or by recycling EN low and high for a short time. OVP can be disabled by grounding the TTSENSE pin. The OVP comparator monitors the output voltage via the CSREF pin.
Reverse Voltage Protection
The VCC supply voltage to the controller must be higher than the UVLO upper threshold, and the EN pin must be higher than its logic threshold so the ADP3207C can begin switching. If the VCC voltage is less than the UVLO threshold, or the EN pin is logic low, then the ADP3207C is in shutdown. In shutdown, the controller holds the PWM outputs at ground, shorts the SS pin capacitor to ground, and drives DCM and OD pins low. Proper power supply sequencing during startup and shutdown of the ADP3207C must be adhered to. All input pins must be at ground prior to applying or removing VCC. All output pins should be left in high impedance state while VCC is off.
Thermal Throttling Control
Very large reverse currents in inductors can cause negative VCore voltage, which is harmful to the CPU and other output components. ADP3207C provides Reverse Voltage Protection (RVP) function without additional system cost. The VCore voltage is monitored through the
The ADP3207C includes a thermal monitoring circuit to detect if the temperature of the variable resistor (VR) has exceeded a user-defined thermal throttling threshold. The thermal monitoring circuit requires an external resistor divider connected between the VCC pin and GND. The divider consists of an NTC thermistor and a resistor. To generate a voltage that is proportional to temperature, the midpoint of the divider is connected to the TTSENSE pin. Whenever the temperature trips the set alarm threshold, an internal comparator circuit compares the TTSENSE voltage to a half VCC threshold and outputs a logic level signal at the VRTT output. The VRTT output is designed to drive an external transistor that, in turn, provides the high current, open drain VRTT signal that is required by the IMVP-6 specification. When the temperature is around the set alarm point, the internal VRTT comparator has a hysteresis of about 100 mV to prevent high frequency oscillation of VRTT. The TTSENSE pin also serves the function of disabling OVP. In extreme heat, users should make sure that the TTSENSE pin voltage remains above 1.0 V if OVP is desired.
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Current Monitor Output
The ADP3207C has an output current monitor. The IMON pin sources a current proportional to the inductor current. A
Table 3. VID Code Table
VID6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1
resistor from IMON pin to FBRTN sets the gain. A 0.1 mF is added in parallel with RMON to filter the inductor ripple. The IMON pin is clamped to prevent it from going above 1.15 V
VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Output (V) 1.5000 1.4875 1.4750 1.4625 1.4500 1.4375 1.4250 1.4125 1.4000 1.3875 1.3750 1.3625 1.3500 1.3375 1.3250 1.3125 1.3000 1.2875 1.2750 1.2625 1.2500 1.2375 1.2250 1.2125 1.2000 1.1875 1.1750 1.1625 1.1500 1.1375 1.1250 1.1125 1.1000 1.0875 1.0750 1.0625 1.0500 1.0375 1.0250 1.0125 1.0000 0.9875 0.9750 0.9625
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Table 3. VID Code Table
VID6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID4 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Output (V) 0.9500 0.9375 0.9250 0.9125 0.9000 0.8875 0.8750 0.8625 0.8500 0.8375 0.8250 0.8125 0.8000 0.7875 0.7750 0.7625 0.7500 0.7375 0.7250 0.7125 0.7000 0.6875 0.6750 0.6625 0.6500 0.6375 0.6250 0.6125 0.6000 0.5875 0.5750 0.5625 0.5500 0.5375 0.5250 0.5125 0.5000 0.4875 0.4750 0.4625 0.4500 0.4375 0.4250 0.4125 0.4000 0.3875 0.3750
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Table 3. VID Code Table
VID6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID5 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output (V) 0.3625 0.3500 0.3375 0.3250 0.3125 0.3000 0.2875 0.2750 0.2625 0.2500 0.2375 0.2250 0.2125 0.2000 0.1875 0.1750 0.1625 0.1500 0.1375 0.1250 0.1125 0.1000 0.0875 0.0750 0.0625 0.0500 0.0375 0.0250 0.0125 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000
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10mF/25V x 8 VDC + + R6 0W C16 1nF Q1 1 IN BST 10 NTMFS4821N DRVH 9 SW 8 GND 7 DRVL 6 U3 ADP3611 NTMSF4846N Q3 NTMSF4846N Q4 R10 C20 C25 L1 360nH/1.1mW 2 SD RTH1 C9 10nF 4 CROWBAR 5 VCC V5S C14 4.7mF NTC 3 DRVLSD C15 1mF VDC RTN C1 C8
NTMFS4821N Q2
330mF/ 6mW x 3 PANASONIC SP SERIES + +
VCC (CORE) 0.3V TO 1.5V 40A VCC (CORE) RTN 10mF x 32 MLCC IN AND AROUND SOCKET
R3 10kW R7 0W C18 1mF Q5 1 IN 2 SD DRVH 9 SW 8 GND 7 DRVL 6 U2 ADP3611 Q7 NTMSF4846N 3 DRVLSD VRTT# 5 VCC C17 4.7mF 4 CROWBAR R4 6.81kW 1% FROM CPU 40 IMON NTMFS4821N BST 10
C19 1nF R11 Q6 L1 360nH/0.85mW NTMFS4821N
VCC (SENSE) VSS (SENSE)
DPRS LPVR VR_ON IMVP6_PWRGD RR 200kW 1%
+ C11 1mF
V3_3S
R1 3kW
R2 3kW VID0 VID1 VID2 VID3 VID4 VID5 VID6 DPRSTP PSI VCC 1
C IMON U1 ADP3207C RSW1*
ADP3207C
RB 1.67kW 1% RRPM 200kW ?% RREF 80.6kW 1% RLIM 5kW 1% RT 604kW 1% R0 C12 1nF CCS1 1.8nF CCS2 2nF RCS1 73.2kW RPH2 84.5kW 1%
RA 39.2kW 1%
IREF ILIMP ILIMN RT RAMP LLINE CSREF CSSUM CSCOMP GND
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EN PWRGD IMON CLKEN FBRTN FB COMP NC RPM DPRSLP TTSENSE VRTT DCM OD PWM1 PWM2 PWM3 SW1 SW2 SW3 RSW2* RPH1 84.5kW 1% RCS2 165kW
CLKEN
0.1mF
CB 330pF
CFB 18pF
CA 220pF
C13 1nF
R5
* FOR A DESCRIPTION OF OPTIONAL COMPONENTS, SEE THE THEORY OF OPERATION SECTION.
Figure 28. Typical 2-Phase Application Circuit
NTMSF4846N Q8
R IMON 5.9kW
RTH2 220kW, 5% NTC
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Application Information The design parameters for a typical Intel IMVP6-compliant CPU core VR application are as follows: * Maximum input voltage (VINMAX) = 19 V * Minimum input voltage (VINMIN) = 7.0 V * Output voltage by VID setting (VVID) = 1.150 V * Maximum output current (IO) = 44 A * Load line slope (RO) = 2.1 mW * Maximum output current step (DIO) = 34.5 A * Maximum output thermal current (IOTDC) = 32 A * Number of phases (n) = 2 * Switching frequency per phase (fSW) = 280 kHz * Duty cycle at maximum input voltage (DMIN) = 0.061 * Duty cycle at minimum input voltage (DMAX) = 0.164
Setting the Clock Frequency for PWM Mode
Equation 3 can be used to determine the minimum inductance based on a given output ripple voltage.
IR + V VID V VID 1 * D MIN f SW RO L (1 * (n f SW D MIN)) V RIPPLE (1 * D MIN) (eq. 3) (eq. 2)
Lw
Solving Equation 3 for a 20 mV peak-to-peak output ripple voltage yields:
Lw 1.150 V 2.1 mW (1 * (2 0.061)) 20 mV (eq. 4) (1 * 0.061) 280 kHz + 356 nH
In PWM mode operation, the ADP3207C uses a fixed-frequency control architecture. The frequency is set by an external timing resistor (RT). The clock frequency and the number of phases determine the switching frequency per phase, which directly relates to switching losses and the sizes of the inductors and input and output capacitors. In a 2-phase design, a clock frequency of 560 kHz sets the switching frequency to 280 kHz per phase. This selection represents a trade-off between the switching losses and the minimum sizes of the output filter components. To achieve a 560 kHz oscillator frequency at VID voltage 1.150 V, RT has to be 237 kW. Alternatively, the value for RT can be calculated using:
RT + V VID ) 1.0 V n f SW 16 pF * 5 kW
(eq. 1)
If the ripple voltage ends up being less than the initially selected value, then the inductor can be changed to a smaller value until the ripple value is met. This iteration allows optimal transient response and minimum output decoupling. The smallest possible inductor should be used to minimize the number of output capacitors. For this example, choosing a 360 nH inductor is a good starting point and gives a calculated ripple current of 10.7 A. The inductor should not saturate at the peak current of 27.4 A and should be able to handle the sum of the power dissipation caused by the average current of 16 A in the winding and core loss. Another important factor in the inductor design is the DCR, which is used to measure phase currents. A large DCR causes excessive power losses, though too small a value leads to increased measurement error. This example uses an inductor with a DCR of 0.89 mW.
Selecting a Standard Inductor
where 16 pF and 5 kW are internal IC component values. For good initial accuracy and frequency stability, it is recommended to use a 1% resistor.
Current Monitor Output
Once the inductance and DCR are known, the next step is to either design an inductor or select a standard inductor that comes as close as possible to meeting the overall design goals. It is also important to have the inductance and DCR tolerance specified to keep the accuracy of the system controlled; 20% inductance and 15% DCR (at room temperature) are reasonable expectations that most manufacturers can meet.
Power Inductor Manufacturers
The IMON pin output a current proportional to the inductor current.
Inductor Selection
The choice of inductance determines the ripple current in the inductor. Less inductance leads to more ripple current, which increases the output ripple voltage and conduction losses in the MOSFETs. However, this allows the use of smaller size inductors, and for a specified peak-to-peak transient deviation, it allows less total output capacitance. Conversely, a higher inductance means lower ripple current and reduced conduction losses but requires larger size inductors and more output capacitance for the same peak-to-peak transient deviation. In a multi-phase converter, the practical peak-to-peak inductor ripple current is less than 50% of the maximum dc current in the same inductor. Equation 2 shows the relationship between the inductance, oscillator frequency, and peak-to-peak ripple current.
The following companies provide surface mount power inductors optimized for high power applications upon request: * Vishay Dale Electronics, Inc. * Panasonic * Sumida Corporation * NEC Tokin Corporation
Output Droop Resistance
The inductor design requires that the regulator output voltage measured at the CPU pins drops when the output current increases. The specified voltage drop corresponds to a dc output resistance (RO). The output current is measured by summing the currents of the resistors monitoring the voltage across each inductor and
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ADP3207C
by passing the signal through a low-pass filter. This summer-filter is implemented by the CS amplifier that is configured with resistors RPH(X) (summer), and RCS and CCS (filter). The output resistance of the regulator is set by the following equations:
RO + R CS R PH(x) RL (eq. 5)
C CS +
L R L @ R CS
(eq. 6)
where RL is the DCR of the output inductors. Users have the flexibility of choosing either RCS or RPH(X). Due to the current drive ability of the CSCOMP pin, the RCS resistance should be larger than 100 kW. For example, users should initially select RCS to be equal to 220 kW, then use Equation 6 to solve for CCS.
C CS + 360 nH 0.89 mW 220 kW + 1.84 nF
The following procedure and equations yield values for RCS1, RCS2, and RTH (the thermistor value at 25C) for a given RCS value: 1. Select an NTC to be used based on type and value. Because there is no value yet, start with a thermistor with a value close to RCS. The NTC should also have an initial tolerance of better than 5%. 2. Based on the type of NTC, find its relative resistance value at two temperatures. Temperatures that work well are 50C and 90C. These are called Resistance Value A (A is RTH (50C)/RTH (25C)) and Resistance Value B (B is RTH (90C)/RTH (25C)). Note the relative value of NTC is always 1 at 25C. 3. Next, find the relative value of RCS that is required for each of these temperatures. This is based on the percentage of change needed, which is initially 0.39%/C. These are called r1 and r2.
r1 + r2 + 1 1 ) TC @ (T 1 * 25) 1 1 ) TC @ (T 2 * 25) (eq. 7)
Because CCS is not the standard capacitance, it is implemented with two standard capacitors in parallel: 1.8 nF and 47 pF. For the best accuracy, CCS should be a 5% NPO capacitor. Next, solve RPH(X) by rearranging Equation 5.
R PH(X) w 0.89 mW 2.1 mW @ 220 kW + 93.2 kW
The standard 1% resistor for RPH(X) is 93.1 kW. To prevent the saturation of the current sense amplifier when multiple phases turn on together, it is recommended to keep RPH(X) > 90 kW in the 2-phase application and RPH(X) > 133 kW in the 3-phase application. To avoid high frequency noise coupling across the RPH resistors, the size of the RPH resistors should not be smaller than the 0603 size.
Inductor DCR Temperature Correction
Where: TC = 0.0039 T1 = 50C T2 = 90C 4. Compute the relative values for rCS1, rCS2, and rTH using:
r CS2 + (A * B) A r CS1 +
1 1*r
r1 (1 * A)
r2 * A
(1 * B)
r2 ) B
(1 * A)
r1
(1 * B) *r
1 *r
r1 * B
(1 * A)
r 2 * (A * B)
CS2
1
CS2
r TH +
1
1 1*r
With the inductor DCR used as a sense element, and copper wire being the source of the DCR, users need to compensate for temperature changes in the inductor's winding. Fortunately, copper has a well-known temperature coefficient (TC) of 0.39%/C. If RCS is designed to have an opposite sign but equal percentage change in resistance, then it cancels the temperature variation of the inductor DCR. Due to the nonlinear nature of NTC thermistors, series resistors, RCS1 and RCS2 (see Figure 29) are needed to linearize the NTC and produce the desired TC tracking.
Place as close as possible to the nearest inductor ADP3207C CSCMOP CSSUM - + CSREF 18 17 19 CCS Keep This Path as Short as Possible and Well Away from Switch Node Lines RTH To Switch Nodes RPH1 RPH2 To VOUT Sense RPH3
CS2
*r
1
CS1
(eq. 8)
5. Calculate RTH = RTH x RCS, then select the closest value of thermistor that is available. Also, compute a scaling factor k based on the ratio of the actual thermistor value relative to the computed one.
k+ R TH(ACTUAL) R TH(CALCULATED) k r CS1 r CS2)) (eq. 10) (eq. 9)
6. Finally, calculate values for RCS1 and RCS2 using:
R CS1 + R CS R CS2 + R CS ((1 * k) ) (k
RCS1
RCS2
Figure 29. Temperature Compensation Circuit Values
This example starts with a thermistor value of 100 kW and uses a Vishay NTHS0603N04 NTC thermistor (a 0603 size thermistor) with A = 0.3359 and B = 0.0771. From this data, rCS1 = 0.359, rCS2 = 0.729, and rTH = 1.094. Solving for RTH yields 240 kW, so 220 kW is chosen, making k = 0.914. Finally, RCS1 and RCS2 are 72.3 kW and 166 kW. Choosing the closest 1% resistor values yields a choice of 71.5 kW and 165 kW.
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COUT Selection
The required output decoupling for processors and platforms is typically recommended by Intel. The following guidelines can also be used if both bulk and ceramic capacitors are in the system: * Select the total amount of ceramic capacitance. This is based on the number and type of capacitors to be used. The best location for ceramics is inside the socket; 20 pieces of Size 0805 being the physical limit. Additional capacitors can be placed along the outer edge of the socket. * Select the number of ceramics and find the total ceramic capacitance (CZ). Combined ceramic values of 200 mF to 300 mF are recommended and are usually made up of multiple 10 mF or 22 mF capacitors. * Note that there is an upper limit imposed on the total amount of bulk capacitance (CX) when considering the VID OTF output voltage stepping (voltage step VV in time tV with error of VERR), and also a lower limit based on meeting the critical capacitance for load release at a given maximum load step DIO. For a step-off load current, the current version of the IMVP-6 specification allows a maximum VCore overshoot (VOSMAX) of 10 mV, plus 1.5% of the VID voltage. For example, if the VID is 1.150 V, then the largest overshoot allowed is 50 mV.
C x(MIN) w n C X(MAX) v L nK 2R
O 2
C X(MIN) w
360 nH @ 34.5 A 2 @ 2.1 mW )
50 mV 34.5 A
* 320 mF + 0.8 mF
@ 1.150 V
C X(MAX) v
360 nH 2 3.1 2 22 ms
220 mV 1.150 V 2 3.1 2.1 mW
2
(2.1 mW) 2 1.150 V 220 mV
1)
360 nH
*1
* 320 mF + 2.3 mF
Using three 330 mF Panasonic SP capacitors with a typical ESR of 6 mW each, yields CX = 0.99 mF with an RX = 2.0 mW. One last check should be made to ensure that the ESL of the bulk capacitors (LX) is low enough to limit the high frequency ringing during a load change. This is tested using:
LX v C2 RO 2 Q2 (2.1 mW) 2 2 + 2 nH (eq. 14) L X v C 320 mF
L RO )
V
DI O
OSMAX
DI
* Cz V VVID (eq. 11)
O
Where: Q is limited to the 2 to ensure a critically damped system. In this example, LX is about 330 pH for the three SP capacitors, which satisfies this limitation. If the LX of the chosen bulk capacitor bank is too large, the number of ceramic capacitors may need to be increased if there is excessive ringing. Note that for this multi-mode control technique, an all-ceramic capacitor design can be used as long as the conditions of Equations 11, 12, and 13 are satisfied.
Power MOSFETs
Vv V VID V VID Vv nKR O L
2
1 ) tv
* 1 * Cz (eq. 12)
where:
K + -1n V ERR VV (eq. 13)
To meet the conditions of these equations and transient response, the ESR of the bulk capacitor bank (RX) should be less than two times the droop resistance, RO. If the CX(MIN) is larger than the CX(MAX), the system does not meet the VID OTF and/or deeper sleep exit specification and can require a smaller inductor or more phases (the switching frequency can also have to be increased to keep the output ripple the same). For example, if using 32 pieces of 10 mF 0805 MLC capacitors (CZ = 320 mF), the fastest VID voltage change is the exit of deeper sleep, and the VCore change is 220 mV in 22 ms with a setting error of 10 mV. Where K = 3.1, solving for the bulk capacitance yields.
For normal 20 A per phase application, the N-channel power MOSFETs are selected for two high-side switches and two low-side switches per phase. The main selection parameters for the power MOSFETs are VGS(TH), QG, CISS, CRSS, and RDS(ON). Because the gate drive voltage (the supply voltage to the ADP3611) is 5.0 V, logic-level threshold MOSFETs must be used. The maximum output current IO determines the RDS(on) requirement for the low-side (synchronous) MOSFETs. In the ADP3207C, currents are balanced between phases; the current in each low-side MOSFET is the output current divided by the total number of MOSFETs (nSF). With conduction losses being dominant, Equation 15 shows the total power dissipated in each synchronous MOSFET in terms of the ripple current per phase (IR) and average total output current (IO):
P SF + (1 * D) )1 12 n SF IO n IR n SF
2
R DS(SF) (eq. 15)
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Knowing the maximum output thermal current and the maximum allowed power dissipation, users can find the required RDS(on) for the MOSFET. For 8-lead SOIC or 8-lead SOIC-compatible packaged MOSFETs the junction to ambient (PCB) thermal impedance is 50C/W. In the worst case, the PCB temperature is 90C during heavy load operation of the notebook; a safe limit for PSF is 0.6 W at 120C junction temperature. Therefore, for this example (32 A maximum thermal current), RDS(SF) (per MOSFET) is less than 9.6 mW for two pieces of low-side MOSFET. This RDS(SF) is also at a junction temperature of about 120C; therefore, the RDS(SF) (per MOSFET) should be lower than 6.8 mW at room temperature, giving 9.6 mW at high temperature. Another important factor for the synchronous MOSFET is the input capacitance and feedback capacitance. The ratio of feedback to input needs to be small (less than 10% is recommended) to prevent accidental turn-on of the synchronous MOSFETs when the switch node goes high. The high-side (main) MOSFET has to be able to handle two main power dissipation components, conduction and switching losses. The switching loss is related to the amount of time it takes for the main MOSFET to turn on and off and to the current and voltage that are being switched. Basing the switching speed on the rise and fall time of the gate driver impedance and MOSFET input capacitance, Equation 16 provides an approximate value for the switching loss per main MOSFETs.
P S(MF) + 2 f SW V CC n MF IO RG n MF n C ISS (eq. 16)
yields 420 mW for each synchronous MOSFET and 410 mW for each main MOSFET. One last consideration is the power dissipation in the driver for each phase. This is best described in terms of the QG for the MOSFETs and is given by:
P DRV + f SW 2 n V CC n MF Q GMF ) n SF Q QSF ) I CC (eq. 18)
Where: QGMF is the total gate charge for each main MOSFET. QGSF is the total gate charge for each synchronous MOSFET. This also shows the standby dissipation (ICC x VCC) of the driver. For the ADP3611, the maximum dissipation should be less than 300 mW, considering its thermal impedance is 220C/W, and the maximum temperature increase is 50C. For this example, with ICC = 2 mA, QGMF = 14 nC, and QGSF = 51 nC, there is 120 mW dissipation in each driver, which is below the 300 mW dissipation limit. Refer to data sheet ADP3611 for more details.
Ramp Resistor Selection
The ramp resistor (RR) is used for setting the size of the internal PWM ramp. The value of this resistor is chosen to provide the best combination of thermal balance, stability, and transient response. Use this equation to determine a starting value:
RR + AR 3 AD 0.5 3 5 L R DS CR + 462 kW (eq. 19)
Where: nMF is the total number of main MOSFETs. RG is the total gate resistance (1.5 W for the ADP3611 and about 0.5 W for two pieces of typical high speed switching MOSFETs, making RG = 2 W). CISS is the input capacitance of the main MOSFET. The best thing to reduce switching loss is to use lower gate capacitance devices. The conduction loss of the main MOSFET is given by:
P C(MF) + D IO n MF
2
RR +
360 nH 5.2 mW 5 pF
)1 12
n
IR
2
n MF
R DS(MF) (eq. 17)
Where: RDS(MF) is the on-resistance of the MOSFET. Typically, for main MOSFETs, users want the highest speed (low CISS) device, but these usually have higher on-resistance. Users must select a device that meets the total power dissipation (0.6 W for a single 8-lead SOIC) when combining the switching and conduction losses. For example, using an IRF7821 device as the main MOSFET (four in total; that is, nMF = 4), with about CISS = 1010 pF (maximum) and RDS(MF) = 18 mW (maximum at TJ = 120C) and an IR7832 device as the synchronous MOSFET (four in total; that is, nSF = 4), RDS(SF) = 6.7 mW (maximum at TJ = 120C). Solving for the power dissipation per MOSFET at IO = 32 A and IR = 10.7 A
Where: AR is the internal ramp amplifier gain. AD is the current balancing amplifier gain. RDS is the total low-side MOSFET on-resistance, CR is the internal ramp capacitor value. Another consideration in the selection of RR is the size of the internal ramp voltage (see Equation 20). For stability and noise immunity, keep this ramp size larger than 0.5 V. In addition, larger ramp size helps to reduce output voltage ringing back during step load transient, where EPWM is triggered. Taking these into consideration, the value of RR is selected as 200 kW. The internal ramp voltage magnitude can be calculated by:
VR + VR + AR RR 0.2 200 kW (1 * D) CR V VID f SW 1.150 V 280 kHz + 0.77 V (eq. 20)
(1 * 0.061) 5 pF
The size of the internal ramp can be made larger or smaller. If it is made larger, then stability and transient response improves, but thermal balance degrades. Likewise, if the ramp is made smaller, then thermal balance improves at the sacrifice of transient response and stability. The factor of three in the denominator of Equation 19 sets a minimum
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ADP3207C
ramp size that gives an optimal balance for good stability, transient response, and thermal balance.
COMP Pin Ramp
There is a ramp signal on the COMP pin due to the droop voltage and output voltage ramps. This ramp amplitude adds to the internal ramp to produce the following overall ramp signal at the PWM input:
V RT + 1*
n
Where: RMON is the current monitor resistor. RMON is connected from IMON pin to FBRTN. RLIM is the current limit resistor. RO is the output load line resistance. IFS is the output current when the voltage on IMON is at full scale.
Current Limit Setpoint
VR
2 f (1*n C D) R
SW
X
O
(eq. 21)
For this example, the overall ramp signal is found to be 2.2 V. Setting the Switching Frequency for RPM Mode Operation of Phase. During the RPM mode operation of Phase 1, the ADP3207C runs in pseudo constant frequency, given that the load current is high enough for continuous current mode. While in discontinuous current mode, the switching frequency is reduced with the load current in a linear manner. When considering power conversion efficiency in light load, lower switching frequency is usually preferred for RPM mode. However, the VCore ripple specification in the IMVP-6 sets the limitation for lowest switching frequency. Therefore, depending on the inductor and output capacitors, the switching frequency in RPM mode can be equal, larger, or smaller than its counterpart in PWM mode. A resistor from RPM to GND sets the pseudo constant frequency as following:
R RPM + 2 RT AR RR (1 * D) CR V VID f SW (eq. 22) V VID ) 1.0 V
To select the current limit setpoint, we need to find the resistor value for RLIM. The current limit threshold for the ADP3207C is set when the current in RLIM is equal to the internal reference current of 20 mA. The current in RLIM is equal to the inductor current times RO. RLIM can be found using the following equation:
R LIM + I LIM RO (eq. 25) 20 mA
Where: RLIM is the current limit resistor. RLIM is connected from the ILIM pin to ground. RO is the output load line resistance. ILIM is the current limit set point. This is the peak inductor current that will trip current limit. In this example, if choosing 55 A for ILIM, RLIM is 5.775 kW, which is close to a standard 1% resistance of 5.76 kW. The per phase current limit described earlier has its limit determined by the following:
I PHLIM ^ V COMP(MAX) * V R * V BIAS AD R DS(MAX) ) IR 2 (eq. 26)
* 0.5 kW
Where: AR is the internal ramp amplifier gain. CR is the internal ramp capacitor value. RR is an external resistor on the RAMPADJ pin to set the internal ramp magnitude. Because RR = 280 kW, the following resistance sets up 300 kHz switching frequency in RPM operation:
R RPM + 2 280 kW 0.5 (1 * 0.061) 5 pF 1.150 300 kHz (eq. 23) 1.150 V ) 1.0 V * 5 W + 202 kW 462 kW
Output Current Monitor
The ADP3207C has output current monitor. The IMON pin sources a current proportional to the total inductor current. A resistor, RMON, from IMON to FBRTN sets the gain of the output current monitor. A 0.1 mF is placed in parallel with RMON to filter the inductor current ripple and high frequency load transients. Since the IMON pin is connected directly to the CPU, it is clamped to prevent it from going above 1.15 V. The IMON pin current is equal to the RLIM times a fixed gain of 10. RMON can be found using the following equation:
R MON + 1.15 V 10 RO R LIM I FS (eq. 24)
For the ADP3207C, the maximum COMP voltage (VCOMP(MAX)) is 3.3 V, the COMP pin bias voltage (VBIAS) is 1.0 V, and the current balancing amplifier gain (AD) is 5. Using a VR of 0.55 V, and a RDS(MAX) of 3.8 mW (low-side on-resistance at 150C) results in a per phase limit of 85 A. Although this number seems high, this current level can only be reached with a absolute short at the output and the current limit latchoff function shutting down the regulator before overheating occurs. This limit can be adjusted by changing the ramp voltage VR. However, users should not set the per phase limit lower than the average per phase current (ILIM/n). There is also a per phase initial duty-cycle limit at maximum input voltage:
D LIM + D MIN V COMP(MAX) * V BIAS VR (eq. 27)
For this example, the duty-cycle limit at maximum input voltage is found to be 0.25 when D is 0.061.
Feedback Loop Compensation Design
Optimized compensation of the ADP3207C allows the best possible response of the regulator's output to a load change. The basis for determining the optimum compensation is to make the regulator and output decoupling appear as an output
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ADP3207C
impedance that is entirely resistive over the widest possible frequency range, including dc, and equal to the droop resistance (RO). With the resistive output impedance, the output voltage droops in proportion with the load current at any load current slew rate. This ensures the optimal positioning and minimizes the output decoupling. With the multi-mode feedback structure of the ADP3207C, users need to set the feedback compensation to make the converter output impedance work in parallel with the output decoupling. Several poles and zeros are created by the output inductor and decoupling capacitors (output filter) that need to be compensated for. A type-three compensator on the voltage feedback is adequate for proper compensation of the output filter. Equations 28 to 36 is intended to yield an optimal starting point for the design; some adjustments can be necessary to account for PCB and component parasitic effects (refer to the Tuning Procedure for ADP3207C section). The first step is to compute the time constants for all of the poles and zeros in the system:
RE + n RO ) AD ) 2 n L R DS ) (1 * n CX RO LX RO CX
R f
The standard values for these components are subject to the tuning procedure, as introduced in the CIN Selection and Input Current DI/DT Reduction section. In continuous inductor current mode, the source current of the high-side MOSFET is approximately a square wave with a duty ratio equal to n x VOUT/VIN and an amplitude of 1-nth the maximum output current. To prevent large voltage transients, a low ESR input capacitor sized for the maximum rms current must be used. The maximum rms capacitor current happens at the lowest input voltage, and is given by:
I CRMS + D IO 1 n 44 A D *1 1 * 1 + 10.3 A 0.164 (eq. 37)
CIN Selection and Input Current DI/DT Reduction
I CRMS + 0.164
2
RL D)
V RT V ID V RT (eq. 28)
In a typical notebook system, the battery rail decouplings are MLCC capacitors or a mixture of MLCC capacitors and bulk capacitors. In this example, the input capacitor bank is formed by eight pieces of 10 mF, and 25 V MLCC capacitors with a ripple current rating of about 1.5 A each.
RC Snubber
V VID RO * R RX
TA + CX
(R O * R ) )
(eq. 29) (eq. 30)
T B + (R X ) R * R O) V RT TC + TD + L* V VID CX CX
A
D
DS
2
SW
RE CZ RO 2 RO
(eq. 31)
Where: R' is the PCB resistance from the bulk capacitors to the ceramics. RDS is the total low-side MOSFET on-resistance per phase. For this example, AD is 5, VRT = 1.5 V, R' is approximately 0.4 mW (assuming an 8-layer motherboard), and LX is 250 pH for the four Panasonic SP capacitors. The compensation values can be solved using the following:
CA + RA + n RO RE TC CA TB RB TD RA (eq. 36) (eq. 35) (eq. 34) TA RB (eq. 33)
(R O * R ) ) C Z
(eq. 32)
It is important in any buck topology to use a resistor capacitor snubber across the low side power MOSFET. The RC snubber dampens ringing on the switch node when the high side MOSFET turns on. The switch node ringing could cause EMI system failures and increased stress on the power components and controller. The RC snubber should be placed as close as possible to the low side MOSFET. Typical values for the resistor range from 1 W to 10 W. Typical values for the capacitor range from 330 pF to 4.7 nF. The exact value of the RC snubber depends on the PCB layout and MOSFET selection. Some fine tuning must be done to find the best values. The equation below is used to find the starting values for the RC subber.
R Snubber + C Snubber + 1 2 p p f Ringing C OSS (eq. 38) (eq. 39) (eq. 40) 1 f Ringing
R Snubber f Swithing
P Snubber + C Snubber
V Input 2
CB +
Where RSnubber is the snubber resistor. CSnubber is the snubber capacitor. fRinging is the frequency of the ringing on the switch node when the high side MOSFET turns on. COSS is the low side MOSFET output capacitance at VInput. This is taken from the low side MOSFET data sheet. Vinput is the input voltage. fSwitching is the switching frequency. PSnubber is the power dissipated in RSnubber.
C FB +
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Selecting Thermal Monitor Components DC Loadline Setting
For single-point hot spot thermal monitoring, simply set RTTSET1 equal to the NTC thermistor's resistance at the alarm temperature (see Figure 30). For example, if the VRTT alarm temperature is 100C using a Vishey thermistor (NTHS-0603N011003J) with a resistance of 100 kW at 25C, and 6.8 kW at 100C, simply set RTTSET1 = RTH1 (100C) to 6.8 kW.
VCC 31 ADP3207C R TTSN 30 CTT + R RTH RTTSET1 5.0 V
3. Measure the output voltage at no load (VNL). Verify that it is within tolerance. 4. Measure the output voltage at full load and at cold (VFLCOLD). Let the board set for ~10 minutes at full load and measure the output (VFLHOT). If there is a change of more than a few mV, then adjust RCS1 and RCS2 using Equations 42 and 43.
R CS2(NEW) + R CS2(OLD) V NL * V FLCOLD V NL * V FLHOT (eq. 42)
VRTT
-
5. Repeat Step 4 until cold and hot voltage measurements remain the same. 6. Measure output voltage from no load to full load using 5 A steps. Compute the load line slope for each change and then average it to get the overall load line slope (ROMEAS). 7. If ROMEAS is off from RO by more than 0.05 mW, use the following to adjust the RPH values:
R PH(NEW) + R PH(OLD) R OMEAS RO (eq. 43)
Figure 30. Single-Point Thermal Monitoring
Multiple-point hot spot thermal monitoring can be implemented as shown in Figure 31. If any of the monitored hot spots reach alarm temperature, the VRTT signal is asserted. The following calculation sets the alarm temperature:
1
R TTSET1 +
2
)
V V
FD
REF REF
V 1 * FD 2 V
R TH1ALARMTEMPERATURE (eq. 41)
8. Repeat Steps 6 and 7 to check load line and repeat adjustments if necessary. 9. Once completed with dc load line adjustment, do not change RPH, RCS1, RCS2, or RTH for the rest of procedure. 10. Measure output ripple at no load and full load with a scope to make sure it is within specification.
AC Loadline Setting
Where VFD is the forward drop voltage of the parallel diode. Because the forward current is very small, the forward drop voltage is very low (100 mV). Assuming the same 100C alarm temperature used in the single-spot thermal monitoring example, and the same Vishay thermistor, then Equation 41 leads to RTTSET = 7.37 kW, whose closest standard resistor is 7.32 kW (1%).
5V VCC 31 R TTSN - + R RTH1 RTH2 RTH3 30 RTTSET1 RTTSET2 RTTSET3
VACDRP VDCDRP
Figure 31. Multiple-Point Thermal Monitoring
Figure 32. AC Loadline Waveform
The number of hot spots monitored is not limited. The alarm temperature of each hot spot can be set differently by playing different RTTSET1, RTTSET2, and RTTSETn. Tuning Procedure for ADP3207C 1. Build the circuit based on compensation values computed from Equations 1 to 41. 2. Hook-up the dc load to the circuit. Turn the circuit on and verify operation. Check for jitter at no load and full load.
11. Remove the dc load from the circuit and hook up the dynamic load. 12. Hook up the scope to the output voltage and set it to dc coupling with the time scale at 100 ms/div. 13. Set the dynamic load for a transient step of about 40 A at 1 kHz with a 50% duty cycle. 14. Measure the output waveform (using the dc offset on scope to see the waveform, if necessary). Try to use the vertical scale of 100 mV/div or finer.
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15. Users should see a waveform that is similar to the one in Figure 33. Use the horizontal cursors to measure VACDRP and VDCDRP as shown. Do not measure the undershoot or overshoot that occurs immediately after the step. 16. If the VACDRP and VDCDRP are different by more than a couple of mV, use the following to adjust CCS. (Note that users may need to parallel different values to get the right one due to the limited standard capacitor values available. It is also wise to have locations for two capacitors in the layout for this.)
C CS(NEW) + C CS(OLD) V ACDRP V DCDRP (eq. 44) VTRANREL
b. For VTRAN1, increase CB or increase switching frequency. c. For VTRAN2, increase RA and decrease CA, both by 25%. 21. For load release (see Figure 34), if VTRANREL is larger than the IMVP-6 specification, there is not enough output capacitance. Either more capacitance is needed or the inductor values need to be smaller. If the inductors are changed, then start the design over using Equations 1 to 38 and this tuning guide.
17. Repeat Step 15 and Step 16. Repeat adjustments if necessary. Once completed, do not change CCS for the rest of the procedure. 18. Set dynamic load step to maximum step size. Do not use a step size larger than needed. Verify that the output waveform is square, which means VACDRP and VDCDRP are equal. Note: Make sure that the load step slew rate and turn-on are set for a slew rate of ~150 A/ms to 250 A/ms (for example, a load step of 50 A should take 200 ns to 300 ns) with no overshoot. Some dynamic loads have an excessive turn-on overshoot if a minimum current is not set properly (this is an issue if using a VTT tool).
Initial Transient Setting
VDROOP
19. With dynamic load still set at the maximum step size, expand the scope time scale to see 2 ms/div to 5 ms/div. A waveform that has two overshoots and one minor undershoot can result (see Figure 33). Here, VDROOP is the final desired value.
Figure 34. Transient Setting Waveform, Load Release
Layout and Component Placement The following guidelines are recommended for optimal performance of a switching regulator in a PC system.
General Recommendations
VDROOP
VTRAN1
VTRAN2
Figure 33. Transient Setting Waveform, Load Step
20. If both overshoots are larger than desired, make the following adjustments in the order they appear. Note that if these adjustments do not change the response, users are limited by the output decoupling. In addition, check the output response each time a change is made, as well as the switching nodes to make sure they are still stable. a. Make ramp resistor larger by 25% (RRAMP).
For effective results, at least a 4-layer PCB is recommended. This allows the needed versatility for control circuitry interconnections with optimal placement, power planes for ground, input and output power, and wide interconnection traces in the rest of the power delivery current paths. Note that each square unit of 1 ounce copper trace has a resistance of ~0.53 mW at room temperature. When high currents need to be routed between PCB layers, vias should be used liberally to create several parallel current paths so that the resistance and inductance introduced by these current paths are minimized, and the via current rating is not exceeded. If critical signal lines (including the output voltage sense lines of the ADP3207C) must cross through power circuitry, a signal ground plane should be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier. An analog ground plane should be used around and under the ADP3207C for referencing the components associated with the controller. Tie this plane to the nearest output decoupling capacitor ground. It should not be tied to any other power circuitry to prevent power currents from flowing in it.
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ADP3207C
The best location for the ADP3207C is close to the CPU corner where all the related signal pins are located: VID0 to VID6, PSI, VCCSENSE, and VSSSENSE. The components around the ADP3207C should be located close to the controller with short traces. The most important traces to keep short and away from other traces are the FB and CSSUM pins (refer to Figure 28 for more details on layout for the CSSUM node.) The MLCC for the VCC decoupling should be placed as close to the VCC pin as possible. In addition, the noise filtering capacitor on the TTSENSE pin should also be as close to that pin as possible. The output capacitors should be connected as closely as possible to the load (or connector) that receives the power (for example, a microprocessor core). If the load is distributed, then the capacitors should also be distributed, and generally in proportion to where the load tends to be more dynamic.
Power Circuitry
Avoid crossing any signal lines over the switching power path loop. This path should be routed on the PCB to encompass the shortest possible length to minimize radiated switching noise energy (that is, EMI) and conduction losses in the board. Failure to take proper precautions often results in EMI problems for the entire PC system as well as noise-related operational problems in the power converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors and the power MOSFETs, including all interconnecting PCB traces and planes. The use of short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high energy ringing, and it accommodates the high current demand with minimal voltage loss. Whenever a power-dissipating component (for example, a power MOSFET) is soldered to a PCB, the liberal use of vias, both directly on the mounting pad and immediately surrounding it, is recommended. Two important reasons for this are: improved current rating through the vias, and improved thermal performance from vias extended to the
ORDERING INFORMATION
Device ADP3207CJCPZ-RL ADP3207CFJCPZ-RL Temperature Range 0C to 100C 0C to 100C
opposite side of the PCB where a plane can more readily transfer the heat to the air. Make a mirror image of any pad being used to heat sink the MOSFETs on the opposite side of the PCB to achieve the best thermal dissipation to the air around the board. To further improve thermal performance, the largest possible pad area should be used. The output power path should also be routed to encompass a short distance. The output power path is formed by the current path through the inductor, the output capacitors, and the load. For best EMI containment, use a solid power ground plane as one of the inner layers extending fully under all the power components. It is important for conversion efficiency that MOSFET drivers, such as ADP3611, are placed as close to the MOSFETs as possible. Thick and short traces are required between the driver and MOSFET gate, especially for the SR MOSFETs. Ground the MOSFET driver's GND pin through the closest vias.
Signal Circuitry
The output voltage is sensed and regulated between the FB pin and the FBRTN pin, which connects to the signal ground at the load. To avoid differential mode noise pickup in the sensed signal, the loop area should be small. Therefore, route the FB and FBRTN traces adjacent to each other atop the power ground plane back to the controller. To filter any noise from the FBRTN trace, using a 1000 pF MLCC is suggested. It should be placed between the FBRTN pin and local ground and as close to the FBRTN pin as possible. Connect the feedback traces from the switch nodes as close as possible to the inductor. The CSREF signal should be Kelvin connected to the center point of the copper bar, which is the VCore common node for the inductors of all phases. On the back side of the ADP3207C package, a metal pad can be used as the device heat sink. In addition, running vias under the ADP3207C is not recommended because the metal pad can cause shorting between vias.
Package LFCSP40 LFCSP40
Shipping 2500 / Tape & Reel 2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *The "Z" suffix indicates Pb-Free part.
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ADP3207C
PACKAGE DIMENSIONS
LFCSP40 6x6, 0.5P CASE 932AC-01 ISSUE A
D D1
PIN ONE REFERENCE
A B
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSIONS: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D1 D2 E E1 E2 e H K L M MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 6.00 BSC 5.75 BSC 3.95 4.25 6.00 BSC 5.75 BSC 3.95 4.25 0.50 BSC --- 12 0.20 --- 0.30 0.50 --- 0.60
E1
E
0.20 C 0.20 C TOP VIEW H 0.10 C
NOTE 4
(A3) A
0.08 C
SIDE VIEW A1 C
SEATING PLANE
SOLDERING FOOTPRINT*
6.30 4.14 1
40X
4X
M
11
D2
K
21
4X
M
0.63
PIN 1 INDICATOR 1 40 31
E2
40X
L
4.14
6.30
e BOTTOM VIEW
40X
b 0.10 C A B 0.05 C
NOTE 3
PACKAGE OUTLINE
0.50 PITCH
0.28
DIMENSIONS: MILLIMETERS
40X
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
FlexMode is a trademark of Analog Devices, Inc. All brand names and product names appearing in this document are registered trademarks or trademarks of their respective holders.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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